1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection structure, and more particularly to an ESD protection structure for carrying and coupling to the electrical devices or printed circuit board.
2. Description of the Related Art
If an electrostatic discharge (ESD) event occurs, an ESD protection structure must quickly transmit a large current (energy) generated by the ESD event to a ground terminal of electrical devices to avoid damage caused by the ESD event. In general, a maximum ESD threat voltage capability (VESD) of the ESD protection structure of electrical devices or systems is determined through an ESD testing experiment which conforms to a testing standard, wherein the maximum ESD threat voltage capability (VESD) corresponds to a maximum ESD treat voltage capability (VESD) supported by the ESD protection structure. In addition, the trigger voltage, clamping voltage, leakage current, parasitic loading effect (capacitance) generated by the protected signals or power loop and related parameters thereof will also determine the protection efficiency of the ESD protection structure.
Harris (U.S. Pat. No. 7,258,819) disclosed conductors, semiconductor particles or combinations thereof doped in a insulating materials (such as FR4 and FR5) of the printed circuit board (PCB) to form a voltage variable material (VVM) substrate, wherein the substrate with VVM can form different types of the ESD protection electrical devices through conventional PCB manufacturing technology. The VVM substrate is in a high impedance state (open circuit/isolation) during normal operation (the ESD event is absent), which functions as an ordinary insulator for carrying the electrical devices or increasing mechanical structural strength of the electrical device package. When an ESD event occurs, the large energy ESD signal will instantaneously activate/polarize the doping particles within the VVM substrate, such that the VVM substrate will be in a low impedance state (short circuit/conduction). Therefore, the low impedance state VVM substrate may transmit the ESD current to the common ground terminal of electrical devices or systems to obtain ESD protection requirement.
Whitney et al. (U.S. Pat. No. 6,351,011) discloses an ESD protection structure for an IC package substrate or semiconductor substrate. Whitney disclosed that a guard rail/ring is formed in a silicon wafer according to process steps (exposure, development and etching etc.), and a VVM is disposed between the guard ring and the I/O pad to enhance ESD protection efficiency of the IC package substrate or semiconductor substrate.
At present, more than one million transistors can be implemented in a single wafer/functional die due to advanced semiconductor process technology (90 nm, 65 nm, 45 nm . . . , etc.), and this enhances performance of the wafer/functional die. In addition, if IC packaging technology is continuously improved along with requirements and the IC package type continues to improve from the pin through hole technology (SIP, DIP etc.) to the surface mount technology (QFP, SOP, BGA, CSP etc.), the physical size of integrated circuit (chip) after packaging can be reduced. Therefore, more chips can be implemented in a single IC package, thus further enhancing electrical device performance. However, providing ESD protection for chips or systems within a limited IC package using the conventional ESD protection methods, is difficult. Specifically, it is difficult to satisfy requirements for higher ESD threat voltage capability (VESD) and lower parasitic loading effect (capacitance). Simultaneously, it is also difficult to apply ESD protection to chips or systems with higher I/O pins. Thus, an ESD protection structure for providing ESD protection function within chips/modules/systems without additional package size (structure) is desired.